As disclosed in JP 2008-52335 A (Patent Literature 1), a semiconductor integrated circuit in which a memory, a logic circuit, and the like are integrated, such as one referred to as a system LSI, is often provided with a memory interface circuit (a memory controller) between the memory and the logic circuit. As exemplarily shown in FIGS. 1, 13, and others of Patent Literature 1, a data signal (DQ) output from a memory (3, 103) is latched by a capture circuit (12, 112) such as a register at timing (a strobe point) defined by a strobe signal (DQS) similarly provided by the memory (3, 103). The strobe point is preferably provided within a period in which the data signal is stable (which is referred to as a window, an eye, or the like) and not near a change point where the data signal changes.
However, a phase of a data signal or the strobe signal may vary as being influenced by an operating environment (a supply voltage, power consumption of the whole semiconductor integrated circuit, an ambient temperature, crosstalk noise of signals passing through nearby signal lines, and the like). Accordingly, the memory interface circuit is often includes an adjustment circuit for adjusting the phase of the data signal or the strobe signal. Patent Literature 1 exemplarily shows a configuration in which an interface circuit (10, 110) includes a variable delay circuit (13, 113) and a delay adjustment circuit (14, 114) for adjusting the phase of the strobe signal (DQS), and a configuration further including a fixed delay circuit (11) for adjusting the phase of the data signal (DQ). A set delay value for the delay adjustment circuit (14, 114) is set by calibration in which the memory (3, 13) and the interface circuit (10, 110) are operated in an adjustment mode at proper timing such as after product assembly, before shipment, or the like (see [0022] and others in Patent Literature 1). Note that, such calibration may be performed every time the semiconductor integrated circuit is turned ON, after test data have been stored in the semiconductor integrated circuit.
As disclosed in Patent Literature 1, in many cases, such calibration is performed in a special operation mode (for example, the above-described adjustment mode). Accordingly, for example when the semiconductor integrated circuit is actually in operation, it is difficult to ascertain such as how much margin (timing margin) is secured between a data signal (actual data) and the strobe point. Depending on the content of the actual data, most of a plurality of data signal lines transmitting data of a plurality of bits may simultaneously vary, inviting an increase in current consumption and in transition time, thereby shifting the phase of the change point. In such a case, a strobe point for a data signal may be set at an undesirable position. Therefore, to become capable of resetting the set delay value, determining whether adjustment is needed, and the like, preferably, such a timing margin and the like can be ascertained while the semiconductor integrated circuit is actually in operation.
Meanwhile, such a mode including a memory and a memory controller is not limited to the above-described system LSI (semiconductor integrated circuit), and may be a multichip module including a plurality of independent chips (including a mode where the chips share a package and each provided with an independent die). In such a mode, a memory chip and a memory controller independent from each other are used, and operate with reference to their respective different clock signals. In many cases, the memory chip includes a phase adjuster for adjusting the phase difference between the clock signal of the memory controller and the clock signal of the memory chip. However, a memory chip used in a smartphone with which recent years have seen proliferation often dispenses with such a phase adjuster to minimize power consumption and costs. Additionally, such a memory chip is relatively low in costs, benefited from mass production. Accordingly, in some cases, such a memory chip is applied to a product other than a smartphone. In such a case, it is more preferable to be capable of ascertaining how much margin (timing margin) is secured between a data signal (actual data) and a strobe point while a multichip module is actually in operation.